The present invention relates generally to the field of electronic clocks, and, more particularly, to distribution of an electronic clock in an electronic circuit, such as an integrated circuit.
The clock distribution network of a microprocessor may use a significant fraction of the total chip power and may have a substantial impact on the overall performance of the microprocessor. For example, the 72-Watt, 600 MHz Alpha processor dissipates approximately 16 Watts in global clock distribution, and another 23 Watts in generating local clocks. Thus, more than half of the Alpha processor's power is used in driving the clock network. Moreover, the uncertainty in a global clock signal may be approximately 10% of the clock period. This may translate into an approximately 10% reduction in maximum operating speed.
Modern microprocessors may use a balanced tree to distribute the clock. Because the delays to all nodes may be nominally equal, a balanced tree may be expected to exhibit relatively low skew. At gigahertz clock speeds, however, an increasing fraction of skew and jitter may come from random variations in gate and interconnect delay. Typically, a relatively large amount of jitter in a clock tree is introduced by buffers and inter-line coupling to the clock wires, and a relatively small amount of jitter may come from noise in the source oscillator. Therefore, conventional clock designs may focus on matching the delay along the various clock paths. As clock speed increases, however, the signal delay across a chip may become comparable to a clock cycle. Because the error in a global clock generally increases in conjunction with an increase in the total path delay, the global clock error may constitute a relatively large fraction of the global clock cycle. Accordingly, there exists a need for improved clock distribution circuits and methods of operating same.